Multilayer stack with compensated resonant circuit

ABSTRACT

A metallization structure in a multilayer stack, which is arranged at a distance from a ground electrode, is characterized in that the metallization structure has a capacitor electrode and a line that acts as a coil, where the capacitor electrode and the line are arranged in a common plane which lies parallel with the ground electrode at a distance h 1 , and in that formula (I) where w is the width of the line.

The invention relates to a metallization structure in a multilayer stackcomprising a number of dielectric layers that are arranged above andbelow a ground electrode.

In current electronic circuits, a very high integration density ofelectrical functions on a small volume or small area is desired. Thismay be achieved, for example, using a three-dimensional circuitarrangement in a multilayer process. In the case of integratedelectrical resonant circuits which are produced using planar technology,for example using multilayer laminate processes and Low TemperatureCofire Ceramic (LTCC) processes, capacitors and coils having metalstructures are incorporated in the multilayer substrate. The integrationof capacitors in such multilayer circuits is nevertheless only possibleto a limited extent. This is because many multilayer processes exhibitfluctuations in the layer thickness, with the statistical fluctuation inlayer thicknesses often being up to 10%, and since the capacitance of aplate capacitor changes as a function of the layer thickness of thedielectric layer between the electrodes an integrated capacitor wouldalso fluctuate by 10% of its capacitance. This leads to correspondingfluctuations in the electrical response of the integrated functions, andthe frequency of a filter designed with integrated coils and capacitorscannot be kept constant in accordance with the specifications. Nowadays,therefore, in multilayer stacks many components are still soldered ontothe circuit as external components, with these being checked for theirset value prior to assembly. The capacitors are sorted in terms of theircapacitance and exhibit variations of typically less than 5%. Theseexternal components limit the miniaturization and entail higher costs onaccount of the assembly. In addition, the soldering process used forthese external components in the assembly has a higher error rate thanwould be the case for integrated capacitors, and thus often leads tofailure of the product.

An alternative solution would be to very carefully monitor the layerthicknesses during the process. However, this is only possible with ahigh level of complexity.

In some circuits, such as the high frequency circuit of a Bluetoothdevice for example, more than ten resonant circuits consisting of acapacitor and a coil are required. The external components required forthese circuits represent a considerable part of the overall number ofexternal components. It would therefore be desirable to integrate theseresonant circuits into a multilayer stack without the variations inlayer thickness brought about by the process having a significant effecton the electrical response of the resonant circuit.

The circuit of FIG. 1( a) shows a grounded series resonant circuit,consisting of a coil L1 and a grounded capacitor C1. At the resonantfrequency of the resonant circuit, a high frequency signal is reflected,since the resonant circuit at this frequency acts as a short circuit.

FIG. 1( b) shows the three-dimensional design of the resonant circuit.

FIG. 1( c) shows the transmission characteristic for a high-frequencysignal for layer thicknesses varying by 10%. The transmissioncharacteristic changes with thickness; in particular the resonantfrequency is shifted.

It is an object of the present invention to provide a metallizationstructure in a multilayer stack having a number of dielectric layers,which metallization structure makes it possible to integrate resonantcircuits into the stack, with layer thickness fluctuations beingcompensated such that they do not or practically do not affect theelectrical response of the resonant circuit.

According to the invention, the metallization structure has a capacitorelectrode and a line that acts as a coil, where the capacitor electrodeand the line are arranged in a common plane which lies parallel to aground electrode at a distance h₁. The ratio of the width w of the lineto h₁ is greater than 3.

According to a preferred refinement, a second ground electrode may beprovided, the common plane with the capacitor electrode and line beingarranged parallel to said second ground electrode at a distance h₂. Thecommon plane with the capacitor electrode and line lies between thefirst and second ground electrodes.

According to the invention, in a multilayer stack having a metallizationstructure as defined above, it is also provided that this metallizationlayer is arranged on a dielectric layer, the dielectric constantε_(medium) of which is greater than the dielectric constant ε of thesurrounding dielectric layers. “Surrounding layers” means the layersadjoining the layer having the dielectric constantε_(medium). Thedielectric constant of such surrounding layers is represented by ε, andthe thickness of such surrounding layers is represented by d_(ε). It hasbeen found that, in such an arrangement, variations in the layerthickness of the dielectric layer having the dielectric constantε_(medium) only very slightly affect the transmission characteristic orthe shift in resonant frequency. If, specifically within the dielectriclayer, the layer thickness decreases, the capacitance of the capacitoris increased. At the same time, the metal line is located closer to theground electrode. This line acts as a coil. At the ground electrode,mirror currents are induced which lower the inductance of the line. Thecloser the line is to the ground electrode, the lower the inductance ofthe line. The product of capacitance and inductance thus remainsapproximately constant and hence so does the resonant frequency

$f = \frac{1}{2\pi\sqrt{L \cdot C}}$of the circuit. Inversely, when the layer thickness increases thecapacitance of the capacitor becomes smaller, while the inductance ofthe line becomes greater. As a result, the product LC again remainsapproximately constant.

According to one preferred refinement, the following applies in respectof the dielectric constantsε≦ε_(medium)

The layer thickness of the dielectric layer d_(medium) having thedielectric constant ε_(medium) should preferably be selected such that

${\frac{ɛ_{medium} \cdot d_{ɛ}}{ɛ \cdot d_{medium}} > 5},$so that the metallization structure that is next in the verticaldirection is well decoupled. In respect of the decoupling in thehorizontal direction, the following should apply

${\frac{ɛ_{medium} \cdot d_{\min}}{d_{medium} \cdot ɛ} > 7},$where d_(min) is the minimum distance to the next metallizationstructure in the plane.

Besides dielectric layers, there may also be magnetic layers in themultilayer stack.

The multilayer stack according to the present invention may be producedin a multilayer laminate process and in particular in an LTCC process.

The invention finds application in electrical modules for implementing afilter function for high frequency signals.

The invention will be further described with reference to examples ofembodiments shown in the drawings to which, however, the invention isnot restricted.

FIG. 1( a) shows a diagram of a conventional series resonant circuit.

FIG. 1( b) shows the three-dimensional design of the conventional seriesresonant circuit of FIG. 1( a).

FIG. 1( c) shows that transmission characteristic of the conventionalseries resonant circuit of FIG. 1( a) in the case of variation of thethickness of the dielectric layer by ±10%.

FIG. 2 shows a multilayer stack and metallization structure according toone example of embodiment of the present invention.

FIG. 3 shows a three-dimensional design of the metallization structurefor making a resonant circuit.

FIG. 4 shows the transmission characteristic of the metallizationstructure in a multilayer stack according to the invention withvariation of the thickness of the dielectric layer having the dielectricconstant ε_(medium) by ±10%.

FIG. 5( a) shows the design of the multilayer stack according to theinvention with an additional ground electrode.

FIG. 5( b) shows the transmission characteristic of the multilayer stackof FIG. 5( a) in comparison with that of FIG. 3.

FIG. 6( a) shows a three-dimensional design of a series resonant circuitaccording to the prior art with additional ground electrode.

FIG. 6( b) shows the transmission characteristic without groundelectrode (I) and with an additional ground electrode (II).

FIG. 7 shows an example of embodiment of a multilayer stack having aresonant circuit between two ground electrodes.

FIG. 2 shows an example of embodiment of a multilayer stack according tothe present invention, which is made up of a number of dielectric layers10, 12, 14, 16, 18, where the dielectric layer 14 on a ground electrode30 has a dielectric constant which is greater, for example by a factorof 2, than the dielectric constants of the surrounding layers 12, 16.The thickness d_(medium) of the dielectric layer 14 is smaller than thatof the surrounding dielectric layers 12, 16 and, in order to keep theinteraction with surrounding structures low, the layer thicknessd_(medium) should advantageously be small compared to the distances toadjacent structures, while εmedium on the other hand should be as greatas possible. It is thus possible for capacitors having sufficientlysmall dimensions to be integrated. A metallization structure 20 isarranged at the interface between the dielectric layer 14 and thedielectric layer 12,the metallization structure being composed of acapacitor electrode 22 and a line 24 that partially surrounds thecapacitor 22. In the illustrated embodiment, w designates the width ofthe line 24, and h₁ designates a distance between the metallizationstructure 20 and the ground electrode 30. Also, in the illustratedembodiment, the ratio of the width w of the line 24 to the distance h₁is greater than 3. In the particular embodiment illustrated in FIG. 2,for the layer 14, d_(medium)=25 μm, and ε_(medium)=20. (Also in theparticular embodiment illustrated in FIG. 5 a, for the layer 14,d_(medium)=25 μm, and ε_(medium)=20.) For adjoining layers 10, 12, 16and 18 above and below, d=100 μm and ε=10.

FIG. 3 shows the three-dimensional (i.e., X, Y, Z directions) design ofthe series resonant circuit structure 20 with the capacitor electrode22, the line 24, and supply lines 26. As shown in FIG. 3, the capacitorelectrode 22 and the supply lines 26 connect to the line 24.

The transmission of power in the circuit according to the invention isshown in FIG. 4. It can clearly be seen that variations of, for example,+10% and −10% in the layer thickness of the dielectric layer 14 leadonly to a very slight change in the resonant frequency or in the overallfilter curve.

The electrical response of the circuit according to the invention hasgreat stability with respect to interaction with other metallizationswhich are located in the multilayer stack above and below the seriesresonant circuit. In the multilayer stack of FIG. 2, above thedielectric layer 12 there is no ground electrode above the metallizationstructure 20. FIG. 5( a) shows the design of this structure with anadditional ground electrode 32 above the metallization structure 20, inaddition to the ground electrode 30 below the metallization structure20. The illustrated metallization structure 20 includes the capacitorelectrode 22 and the line 24, as described above. In the illustratedembodiment, w designates the width of the line 24, h₂ designates adistance between the metallization structure 20 and the additionalground electrode 32, and the ratio of the width w of the line 24 to thedistance h₂ is greater than three. FIG. 5( b) shows the transmissioncharacteristic, where without a ground electrode (curve I) and atdifferent distances of the additional ground electrode of 100 μm (curveII) and 200 μm (curve III) practically no variations in the resonantfrequency can be seen. This effect is based on the high degree ofcoupling of the metallization structure 20 according to the invention tothe ground electrode 30 (see FIG. 5( a)) arranged at a small distanceand the advantageously relatively high dielectric constant compared tothat of the surrounding layers.

For comparison purposes, in FIG. 6( a) a resonant circuit withmultilayer stack according to the prior art or as shown in FIG. 1( b) islikewise provided with a further ground electrode at a vertical distanceof 100 μm above the circuit. The transmission characteristic II in FIG.6( b) shows that the upper electrode leads to a considerable shift inthe resonant frequency compared to the arrangement without an additionalground electrode (curve I).

FIG. 7 shows a multilayer stack having two ground electrodes 30, 32,between which the metallization structure 20 is arranged, where betweenthe metallization structure 20 and the ground electrodes 30 and 32 ineach case dielectric layers 14 and 14′, respectively, having increaseddielectric constants compared to that of the surrounding layers 12, 16are provided. Otherwise, the multiplayer stack corresponds essentiallyto that of FIG. 2, having other similar dielectric layers 10 and 18, asdescribed above. Additionally, the metallization structure 20 includes acapacitor electrode 22 and a line 24, as described above. In theillustrated embodiment, for the layers 14 and 14′, d_(medium)=25 μm, andε_(medium)=20.

1. A multilayer stack comprising: a dielectric layer and one or moresurrounding dielectric layers situated above or below the dielectriclayer, a dielectric constant of the dielectric layer being greater thana dielectric constant of the surrounding dielectric layers, and ametallization structure which is arranged on the dielectric layer and isarranged at a distance from a ground electrode, wherein themetallization structure has a capacitor electrode and a line that actsas a coil, where the capacitor electrode and the line are arranged in acommon plane which lies parallel to the ground electrode at a distanceh₁, and wherein: ${\frac{w}{h_{1}} > 3},$  where w is the width of theline, wherein: $\frac{ɛ_{medium} \cdot d_{ɛ}}{ɛ \cdot d_{medium}} > 5$ wherein the dielectric constant of and a thickness of the dielectriclayer are ε_(medium) and d_(medium), respectively, and the dielectricconstant of and a thickness of the surrounding dielectric layers are εand d_(ε), respectively.
 2. A metallization structure as claimed inclaim 1, further comprising: a second ground electrode, the common planecomprising the capacitor electrode and the line being arranged parallelto said second ground electrode at a distance h₂, and the common planecomprising the capacitor electrode and the line being between the firstand second ground electrodes, where $\frac{w}{h_{2}} > 3.$
 3. Amultilayer stack as claimed in claim 2, further comprising one or moreadditional metallization structures in the common plane, wherein${\frac{ɛ_{medium} \cdot d_{\min}}{ɛ \cdot d_{medium}} > 7},$ whered_(min) is the minimum distance to a nearest metallization structure inthe plane, and wherein the dielectric constant of and a thickness of thedielectric layer are ε_(medium) and d_(medium), respectively, and thedielectric constant of the surrounding dielectric layers is ε.
 4. Amultilayer stack as claimed in claim 2, wherein the multilayer stackfurther comprises magnetic layers.
 5. A multilayer stack as claimed inclaim 2, produced in a multilayer laminate process.
 6. A multilayerstack as claimed in claim 2, produced in a Low Temperature CofireCeramic (LTCC) process.
 7. A multilayer stack comprising: a dielectriclayer and one or more surrounding dielectric layers situated above orbelow the dielectric layer, a dielectric constant of the dielectriclayer being greater than a dielectric constant of the surroundingdielectric layers, and a metallization structure which is arranged onthe dielectric layer and is arranged at a distance from a groundelectrode, wherein the metallization structure has a capacitor electrodeand a line that acts as a coil, where the capacitor electrode and theline are arranged in a common plane which lies parallel to the groundelectrode at a distance h₁, and wherein: ${\frac{w}{h_{1}} > 3},$  wherew is the width of the line, wherein the multilayer stack is produced ina Low Temperature Cofire Ceramic (LTCC) process.
 8. A metallizationstructure as claimed in claim 7, further comprising: a second groundelectrode, the common plane comprising the capacitor electrode and theline being arranged parallel to said second ground electrode at adistance h₂, and the common plane comprising the capacitor electrode andthe line being between the first and second ground electrodes, where$\frac{w}{h_{2}} > 3.$
 9. A multilayer stack as claimed in claim 8,further comprising one or more additional metallization structures inthe common plane, wherein${\frac{ɛ_{medium} \cdot d_{\min}}{ɛ \cdot d_{medium}} > 7},$ whered_(min) is the minimum distance to a nearest metallization structure inthe plane, and wherein the dielectric constant of and a thickness of thedielectric layer are ε_(medium) and d_(medium), respectively, and thedielectric constant of the surrounding dielectric layers is ε.
 10. Amultilayer stack as claimed in claim 8, wherein the multilayer stackfurther comprises magnetic layers.
 11. A multilayer stack as claimed inclaim 8, produced in a multilayer laminate process.
 12. A multilayerstack comprising: a dielectric layer and one or more surroundingdielectric layers situated above or below the dielectric layer, adielectric constant of the dielectric layer being greater than adielectric constant of the surrounding dielectric layers; ametallization structure which is arranged on the dielectric layer and isarranged at a distance from a ground electrode, wherein themetallization structure has a capacitor electrode and a line that actsas a coil, where the capacitor electrode and the line are arranged in acommon plane which lies parallel to the ground electrode at a distanceh₁, and wherein ${\frac{w}{h_{1}} > 3},$ where w is the width of theline; a second ground electrode, the common plane comprising thecapacitor electrode and the line being arranged parallel to said secondground electrode at a distance h₂, and the common plane comprising thecapacitor electrode and the line being between the first and secondground electrodes, where ${\frac{w}{h_{2}} > 3};{and}$  one or moreadditional metallization structures in the common plane, wherein${\frac{ɛ_{medium} \cdot d_{\min}}{ɛ \cdot d_{medium}} > 7},$  whered_(min) is the minimum distance to a nearest metallization structure inthe plane, and wherein the dielectric constant of and a thickness of thedielectric layer are ε_(medium) and d_(medium), respectively, and thedielectric constant of the surrounding dielectric layers is ε.
 13. Themultilayer stack of claim 12,$\frac{ɛ_{medium} \cdot d_{ɛ}}{ɛ \cdot d_{medium}} > 5$ wherein thedielectric constant of and a thickness of the dielectric layer areε_(medium) and d_(medium), respectively, and the dielectric constant ofand a thickness of the surrounding dielectric layers are ε and d_(ε),respectively.
 14. The multilayer stack of claim 12, wherein themultilayer stack further comprises magnetic layers.
 15. The multilayerstack of claim 12, wherein the multilayer stack is produced in amultilayer laminate process.
 16. The multilayer stack of claim 12,wherein the multilayer stack is produced in a LTCC process.
 17. Amultilayer stack comprising: a dielectric layer and one or moresurrounding dielectric layers situated above or below the dielectriclayer, a dielectric constant of the dielectric layer being greater thana dielectric constant of the surrounding dielectric layers; ametallization structure which is arranged on the dielectric layer and isarranged at a distance from a ground electrode, wherein themetallization structure has a capacitor electrode and a line that actsas a coil, where the capacitor electrode and the line are arranged in acommon plane which lies parallel to the ground electrode at a distanceh₁, and wherein ${\frac{w}{h_{1}} > 3},$  where w is the width of theline; a second ground electrode, the common plane comprising thecapacitor electrode and the line being arranged parallel to said secondground electrode at a distance h₂, and the common plane comprising thecapacitor electrode and the line being between the first and secondground electrodes, where ${\frac{w}{h_{2}} > 3};{and}$  magnetic layers.18. The multilayer stack of claim 17,$\frac{ɛ_{medium} \cdot d_{ɛ}}{ɛ \cdot d_{medium}} > 5$ wherein thedielectric constant of and a thickness of the dielectric layer areε_(medium) and d_(medium), respectively, and the dielectric constant ofand a thickness of the surrounding dielectric layers are ε and d_(ε),respectively.
 19. The multilayer stack of claim 17, wherein themultilayer stack is produced in a multilayer laminate process.
 20. Themultilayer stack of claim 17, wherein the multilayer stack is producedin a LTCC process.